This invention relates to a digital filter system, which is provided in an information transmission system and comprises a plurality of digital filters including respective counters operated by the same clock signal.
Digital filters have similar functions to those of analog filters except for that they execute operations to obtain digital values. Where the speed of operation of such digital filters is sufficiently high compared to the speed of input signal sampling, effective utility of these digital filters is possible by incorporating multi-filter arrangement of multi-channel arrangement, these arrangements using a filter circuit based upon a time division basis, or combination of such arrangements. In the multi-filter arrangement, a higher order filter is constituted by repeatedly processing a single input signal through unit blocks of lower order filters (usually of the second order and of cascade connection or parallel connection). However, limitations are imposed upon this multiplex construction by such factors as the upper limit of the operation speed of the unit block, and lower limit of the data sampling speed and the required order of the digital filter (determined by the characteristics of the required filters). From this ground, it is sometimes necessary to use a plurality of digital filters.
In the multi-channel arrangement, a plurality of independent channel signals are processed with a single digital filter. Again in this case, however, it is sometimes necessary to use a plurality of digital filters from the same grounds as in the case of the multi-filter arrangement.
In such cases as above where a plurality of digital filters are employed in an information transmission system, it is usually necessary to provide synchronization among these filters. It is in usual practice in the digital filter to externally supply a clock signal as reference signal and produce various gate signals and clock signals required for the operations within the filter. To this end, however, a considerable number of arithmetic control circuits are required particularly in the aforementioned multiplex construction. In this case, unless the individual arithmetic control circuits of the digital filters are synchronized to one another, erroneous transmission and reception of signals among the mutual digital filters are liable, thus giving rise to malfunction and erroneous operations.
Accordingly, it is contemplated to supply, for instance, a start signal, i.e., initial clear signal, simultaneously to these digital filters for synchronization. With this method, however, once departure from the synchronization results due to noise or other causes, the subsequent operations are totally done erroneously so that normal filter function is no longer obtained. In addition, with this method unless the start signal is given in exact synchronism to the clock signal, the content of the counter within each digital filter is likely to be shifted by one pulse due to the difference in sensitivity among the elements of flip-flops constituting the counter, and this also causes lowering of the filter function.